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Integrated Circuit Systems, Inc.
ICS9179-06
Zero Delay Buffer for PC133 SDRAMs
General Description
The ICS9179-06 generates low skew SDRAM clocks required by high-speed RISC or CISC based microprocessor systems. The ICS9179-06 is a zero delay buffer with low output-to-output skew. The buffer is compatible with Spread Spectrum clocks such as those provided by the ICS 9248-55. Individual outputs can be disabled via the I2C interface for reduced power consumption and EMI. The nominal delay for the ICS9179-06 can also be programmed to either 0.0, -2.6, +2.1 or -0.7 ns via the I2C interface. An output enable pin eases testability.
Features
* * * * * * * * * * * *
16-out zero delay buffer Supports up to 4 PC133 SDRAM DIMMs Spread Spectrum compatible I2C Interface Four nominal input-to-output delays from +2.1 to -2.6 ns selectable via I2C 250 ps output-to-output skew 33 MHz to 133 MHz operating frequency Multiple VDD, VSS pins for noise reduction 1.5V/ns minimum slew rate into 30 pF load VDD = 3.3V +/-5%, Commercial temperature range All outputs except FB_OUT tri-state with OE low. 48-pin SSOP package
Block Diagram
Pin Configuration
6
1
Functionality
OE# 0 1 OUTPUT (0:15) Hi-Z 1 X INPUT FB_OUT 1 X INPUT 1 X INPUT
48-Pin SSOP
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Pin Descriptions
PIN NUMBER 2 5, 6, 9, 10 15, 16, 19, 20 29, 30, 33, 34 40, 41, 44, 45 12 13 24 25 37 3, 7, 11, 17, 21, 31, 35, 38, 42, 46 4, 8, 14, 18, 28, 32, 36, 39, 43, 47 22 23 26 27 1, 48 PIN NAME OE OUTPUT (0:3) OUTPUT (4:7) OUTPUT (8:11) OUTPUT (12:15) INPUT FB_IN SDATA SCLK FB_OUT VDD GND VDDA VDDS GNDS GNDA N/C TYPE IN OUT OUT OUT OUT IN IN I/O I/O OUT PWR PWR PWR PWR PWR PWR DESCRIPTION Tr i-states all outputs except FB_OUT when held LOW. Has inter nal pull-up.2 S D R A M B y t e 0 c l o ck o u t p u t s 1 SDRAM Byte 1 clock outputs1 SDRAM Byte 2 clock outputs1 S D R A M B y t e 3 c l o ck o u t p u t s 1 Input for reference clock. Feedback input. Data pin for I2C circuitr y3 Clock pin for I2C circuitr y3 Feedback output to input FB_IN. 3.3V Power supply for output buffers Ground for output buffers 3.3V Power supply for Analog PLL stages 3.3V Power supply for I2C circuitr y Ground for I2C circuitr y Ground for Analog PLL stages Pins are not inter nally connected
Notes: 1. At power up all sixteen outputs are enabled and active. 2. OE has a 100K Ohm internal pull-up resistor to keep all outputs active. 3. The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for complete platform flexibility. 4. I2C Byte0, bits 0 & 1 used to select delay. Default* values at power up are 0
Power Groups
VDD = Power supply for OUTPUT buffers VDDS = Power supply for I2C circuitry VDDA = Power supply for Analog PLL circuitry
Delay Selection Table
INPUT Control Byte0 bit1 0* 0 1 1 FB_IN Control Byte0 bit0 0* 1 0 1 Nominal Delay, INPUT to FB_IN pins. 0ns -2.7ns +2.0ns -0.7ns
Ground Groups
GND = Ground supply for OUTPUT buffer GNDS = Ground supply for I2C circuitry GNDA = Ground supply for Analog PLL circuitry
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ICS9179-06
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
Byte 1
ACK
Byte 1
ACK
Byte 2
ACK
Byte 2
ACK
Byte 3
ACK
Byte 3
ACK
Byte 4
ACK
Byte 4
ACK
Byte 5
ACK
Byte 5
ACK
Stop Bit
ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9179-06
Serial Configuration Command Bitmaps
Byte 0: OUTPUT Clock Register (default = 0)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 12 Bit 02 PIN# PWD 0 0 0 0 0 0 12 0 13 0 DESCRIPTION Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved (See Delay Selection Table) (See Delay Selection Table)
Byte 1: OUTPUT Clock Register
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# PWD 20 1 19 1 16 1 15 1 10 1 9 1 6 1 5 1
DESCRIPTION OUTPUT 7 (Act/Inact) OUTPUT 6 (Act/Inact) OUTPUT 5 (Act/Inact) OUTPUT 4 (Act/Inact) OUTPUT 3 (Act/Inact) OUTPUT 2 (Act/Inact) OUTPUT 1 (Act/Inact) OUTPUT 0 (Act/Inact)
Notes: 2 = Default = 0; 1 = Delay element enabled, 0 = No delay path.
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default Byte (3:5): Reserved
Byte 2: OUTPUT Clock Register (Default = 1)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 45 44 41 40 34 33 30 29 PWD 1 1 1 1 1 1 1 1 DESCRIPTION OUTPUT 15 (Act/Inact) OUTPUT 14 (Act/Inact) OUTPUT 13 (Act/Inact) OUTPUT 12 (Act/Inact) OUTPUT 11 (Act/Inact) OUTPUT 10 (Act/Inact) OUTPUT 9 (Active/Inactive) OUTPUT 8 (Active/Inactive)
BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1
DESCRIPTION Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
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ICS9179-06
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input & Supply
TA = 0 - 70C; Supply Voltage V DD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Current Standby Current Input frequency Input Duty Cycle Input Capacitance
1
SYMBOL VIH V IL I IH I IL1 I IL2 I DD
CONDITIONS
MIN 2 V S S- 0.3 -5 -60
TYP
V IN = VDD V IN = 0 V; Inputs V IN = 0 V; Inputs CL = 0 pF; FIN @ CL = 0 pF; FIN @ CL = 0 pF; FIN @
with no pull-up resistors with pull-up resistors 66MHz 100MHz 133.33MHz
-33 115 170 220
MAX UNITS V DD + 0.3 V 0.8 V 5 uA uA uA 150 mA 190 mA 270 mA 30 mA MHz % pF
I DDSB FIN DI CIN
CL = 0 pF; 33.33MHz FIN 133.33MHz Outputs Disabled 33.33MHz FIN 133.33MHz Logic Inputs 33.33 40
133.33 60 5
Guaranteed by design and characterization, not 100% tested in production.
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ICS9179-06
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V PARAMETER SYMBOL Output Frequency FO Output High Voltage VOH Output Low Voltage VOL Output High Current IOH Output Low Current IOL Rise Time Tr Fall Time Tf Duty Cycle Dt Output to Output Tsk Skew Window Tskd1 IN to FB_IN Skew1, 2 Tskd2 Tskd3 Tskd4 +/-5%; CL = 20 - 30 pF (unless otherwise CONDITIONS IOH = -30 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V, default Zero delay, I2C B0 bits 0, 1 = 00 VT = 1.5 V bits 0, 1 = 10 VT = 1.5 V bits 0, 1 = 01 VT = 1.5 V bits 0, 1 = 11 -250 -2.2 +1.5 -0.2 0 -2.6 +2.1 -0.7 MIN 33 2.4 TYP MAX UNITS 133 MHz V 0.4 V -54 mA mA 1.33 ns 1.33 ns 55 % 250 250 -3.2 +2.5 -1.2 ps ps ns ns ns
40
45
Notes: 1. Guarenteed by design and characterization, not 100% tested in production 2. Delay elements FBIN and clock INPUT path are selected by I2C BYTE2; bit 0 = clock input control, bit 1 = Clock INPUT Control. (Default is 0). A 0 = No delay in path, 1 = Delay element selected.
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ICS9179-06
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs.
Capacitor Values: All unmarked capacitors are 0.01F ceramic
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ICS9179-06
SSOP Package
SYMBOL A A1 A2 B C D E e H h L N X COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100 VARIATIONS AC MIN. .620 D NOM. .625 N MAX. .630 48
Ordering Information
ICS9179F-06
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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